1. Field
Exemplary embodiments of the present invention relate to a precharge circuit for supplying a precharge voltage to a data line.
2. Description of the Related Art
An integrated circuit chip that inputs/outputs data through a data line uses a precharge circuit in order to precharge the data line for the next operation after completing a data input operation or a data output operation.
FIG. 1 is a schematic diagram illustrating a conventional non-volatile memory device including a precharge circuit. The conventional non-volatile memory device shown in FIG. 1 includes a plurality of page buffers 10_0 to 10_N, a precharger 20, and a sense amplifier 30.
The precharger 20 applies the voltage of a precharge voltage terminal PVND to a positive local input/output line LIO and a negative local input/output line LIOB during a precharge operation. FIG. 1 illustrates a case that a core voltage VCC is supplied as the voltage of the precharge voltage terminal PVND. To be specific, in a duration when a precharge signal is in a logic high level (which is a duration when an second inverted precharge signal PCGB is in a logic low level), the voltage VCC of the precharge voltage terminal PVND is applied to the positive local input/output line LIO and the negative local input/output line LIOB. The second inverted precharge signal PCGB is a signal whose phase is in opposite to the precharge signal. Therefore, the voltage levels of the positive local input/output line LIO and the negative local input/output line LIOB become the same as the voltage level of the core voltage VCC during a precharge operation.
The page buffers 10_0 to 10_N perform a program operation for storing data D0 to DN in a memory cell array (not shown) and a read operation for reading the data D0 to DN out of the memory cell array (not shown). Each of the page buffers 10_0 to 10_N illustrated in FIG. 1 includes a latch which is formed of two inverters I1 and I2. The page buffers 10_0 to 10_N latch the data D0 to DN that are read out of the memory cell array (not shown), and when a column selection signal CS<0:N> is enabled, the page buffers 10_0 to 10_N transfer the latched data D0 to DN to the positive local input/output line LIO and the negative local input/output line LIOB. The column selection signal CS<0:N> is generated by a column decoder 15 illustrated in FIG. 2. In other words, the column decoder 15 generates the column selection signal CS<0:N> by decoding an inputted column address CA<0:M> and the column selection signal CS<0:N> is enabled to a logic high level, which is the voltage level of the core voltage VCC, based on the column address CA<0:M>.
The sense amplifier 30 senses the voltage level difference between the positive local input/output line LIO and the negative local input/output line LIOB, amplifies the data, and transfers the amplified data to a global data input/output line GIO.
FIG. 3A is a timing diagram illustrating a read operation of the non-volatile memory device shown in FIG. 1 when no power drop occurs in the voltage level of a precharge voltage terminal PVND.
The second inverted precharge signal PCGB is in a logic low level in a precharge duration TPCG. PMOS transistors P1 and P2 of the precharger 20 are turned on in response to the second inverted precharge signal PCGB of the a logic low level, and the voltage VCC of the precharge voltage terminal PVND is applied to the positive local input/output line LIO and the negative local input/output line LIOB. Therefore, the voltage levels of the positive local input/output line LIO and the negative local input/output line LIOB become the core voltage VCC in the precharge duration TPCG.
The second inverted precharge signal PCGB transitions to a logic high level in a sensing duration TSEN. The PMOS transistors P1 and P2 of the precharger 20 are turned off in response to the second inverted precharge signal PCGB of a logic high level. Therefore, the voltage VCC of the precharge voltage terminal PVND is not applied to the pair of the positive local input/output line LIO and the negative local input/output line LIOB anymore.
Meanwhile, column selection signals CS<0:N> are generated as an inputted column address CA<0:M> is decoded, and among the generated column selection signals CS<0:N>, a column selection signal corresponding to a page buffer designated by the column address CA<0:M> is enabled to a logic high level in the sensing duration TSEN. FIG. 3A shows a case that the 0th column selection signal CS<0> is enabled to a logic high level in the sensing duration TSEN. When the 0th column selection signal CS<0> is enabled to a logic high level, NMOS transistors N1 and N2 of the 0th page buffer 10_0 that corresponds to the 0th column selection signal CS<0> are turned on to transfer data D0 and /D0 that are latched in the 0th page buffer 10_0 to the positive local input/output line LIO and the negative local input/output line LIOB. Hereinafter, for the description purposes, a case that the data D0 latched in the 0th page buffer 10_0 is in a logic high level (which is a case that the inverted data /D0 is in a logic low level) is described as a example. The NMOS transistor N1 is turned on in response to the 0th column selection signal CS 0> of a logic high level, and the inverted data /D0 is transferred to the negative local input/output line LIOB. Since the inverted data /D0 of a logic low level, which is a ground voltage VSS, is transferred to the negative local input/output line LIOB, the voltage level of the negative local input/output line LIOB drops.
On the contrary, the voltage level of the positive local input/output line LIO to which the data D0 of the same logic high level as the core voltage VCC is transferred through the NMOS transistor N2 of the 0th page buffer 10_0 maintains the voltage level of the core voltage VCC.
For this reason, voltage level difference dV is caused between the positive local input/output line LIO and the negative local input/output line LIOB, and the sense amplifier 30 amplifies the data by sensing the voltage level difference dV between the positive local input/output line LIO and the negative local input/output line LIOB in response to an amplification enabling signal SA_EN, that is enabled to a logic high level, and transfers the amplified data to a global data input/output line GIO.
Meanwhile, if the voltage level VCC of the precharge voltage terminal PVND is not maintained at a constant level, it is not sure whether the sensing operation is performed accurately. In particular, since the non-volatile memory device simultaneously accesses the data of the memory cell array (not shown) on the basis of a page by using the multiple page buffers 10_0 to 10_N, it consumes much current and this leads to a power drop. If the voltage level of the precharge voltage terminal PVND of the precharger 20 drops due to the simultaneous access of the page buffers 10_0 to 10_N to the data of the memory cell array (not shown), the voltage level difference dV between the positive local input/output line LIO and the negative local input/output line LIOB may not be adequate for making sure a stable sensing operation. This is described in detail with reference to FIG. 3B.
FIG. 3B is a timing diagram illustrating a read operation of the non-volatile memory device shown in FIG. 1 when a power drop occurs in the voltage level of the precharge voltage terminal PVND in the precharge duration TPCG. For the description purposes, FIG. 33 shows a case that the core voltage VCC is supplied as the voltage of the precharge voltage terminal PVND.
When a power drop occurs in the core voltage VCC in the precharge duration TPCG, the precharger 20 applies the decreased core voltage VCC to the positive local input/output line LIO and the negative local input/output line LIOB. As a result, the voltage levels of the positive local input/output line LIO and the negative local input/output line LIOB drop as the core voltage VCC has dropped.
When the 0th column selection signal CS<0> is enabled to a logic high level and the inverted data /D0 of a logic low level is transferred to the negative local input/output line LIOB in the sensing duration TSEN, the voltage level of the negative local input/output line LIOB is decreased even lower. Since the voltage level of the positive local input/output line LIO has been also lowered due to the power drop occurring in the core voltage VCC, which is the precharge voltage, the voltage level difference dV between the positive local input/output line LIO and the negative local input/output line LIOB is too small to perform a sensing operation as illustrated in FIG. 3B. Here, the minimum voltage level difference dV between the ends of the positive local input/output line LIO and the negative local input/output line LIOB at which the sense amplifier 30 may perform a sensing operation is referred to as an offset. The offset of the sense amplifier 30 may be generated by mismatch of the sense amplifier 30. As illustrated in FIG. 3B, if the voltage level difference dV between the ends of the positive local input/output line LIO and the negative local input/output line LIOB of a pair may not be secured more than the offset, the sense amplifier 30 may not perform a sensing operation accurately.